Generally, semiconductor devices include a plurality of circuits that form an integrated circuit including chips (e.g., chip back end of line, or “BEOL”), thin film packages and printed circuit boards. Integrated circuits (ICs) can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits are increased. Thus, the formation of multilevel or multilayered interconnect schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (k) organosilicate glass (OSG) dielectric layer that includes atoms of Si, C, H and O, and the fatwires are made in a silicon dioxide dielectric layer having a dielectric constant of about 4.
For future technology nodes, the integration of porous (OSG) materials into Cu/ULK interconnect structures becomes necessary for maintaining the ITRS roadmap for increased performance. Essentially, since materials of dielectric constants in the range 2.7 to 3.1 are either in production (90 nm) or about to enter into production (65 nm), in order to continue to deliver performance enhancing interconnect solutions for various CMOS technologies, integrating ULK materials for beyond 65 nm node will be necessary. However, these materials of dielectric constant less than 2.7 are quite susceptible to plasma-induced chemical/physical modification (“damage”) upon exposure to resist removal plasma ashing chemistries and typically manifest poor adhesion to inter-level diffusion barrier materials (SiC, SiCN, SiCNH, and etc.).
A typically prior art process for forming a dual damascene interconnect structure is shown, for example, in FIGS. 1A-1D. FIG. 1A shows the interconnect structure after providing a patterned photoresist 20 to a material stack 15 that comprises a hard mask 16 and an overlaying antireflective coating 18. The interconnect structure also includes an ULK OSG dielectric 14, a diffusion barrier 12 and a substrate layer 10. The substrate layer 10 may comprise a semiconductor substrate having one or more semiconductor devices located thereon, or it may comprise one of the lower interconnect levels which may have conductive features, i.e., wires and/or vias located therein.
FIG. 1B shows the structure of FIG. 1A after transferring the pattern (via first and then line) from the patterned photoresist 20 into the material stack 15 and the underlying ULK OSG dielectric 14 and providing an organic fill material 22 within lower portions of a trench opening 24. The trench opening 24 includes an upper area A that is wider than a lower area B.
FIG. 1C shows the structure of FIG. 1B after performing an ashing step which removes the patterned photoresist 20, the ARC 18 and the organic fill material 22 from the interconnect structure. FIG. 1D shows the structure after opening the diffusion barrier 12 utilizing an etching process that is selective in removing the exposed portions of the diffusion barrier 12. It is noted that wall portions of the OSG dielectric 14 within the trench opening 24 are damaged. By ‘damaged’ it is meant that the wall portions of the OSG dielectric 14 within the trench opening 24 that are exposed to the ashing plasma are modified from an original composition to one that is more oxide- or oxynitride-like. The damaged portions are labeled as element 26 in FIG. 1D. The damaged portions 26 typically have a different (i.e., increased) dielectric constant as compared with the remaining portions of the OSG dielectric 14.
To address the issue of plasma-induced “damage” several alternative resist removal plasma ash chemistries (reducing plasmas) have been proposed. See, for example, U.S. Pat. No. 6,630,406. All of these alternative chemistries nonetheless do modify the OSG dielectric material to some degree increasing the film's dielectric constant and degrading the overall interconnect performance (though potentially at target for a given technology node).
Another approach utilizes alternative integration schemes (so-called “trench-first”) to circumvent this issue whereby after patterning part of the line structure, all resist is removed (with the OSG dielectric still protected by various hard mask materials) and thereafter some hard mask material (metallic or non-metallic) serves as the pattern transfer layer. More details of one such alternative scheme can be found, for example, in U.S. Pat. No. 6,734,096 and U.S. patent application Ser. No. 11/034,480.
Such integration schemes, though successfully addressing the issue of plasma ash-induced ILD modification, sometimes offer a narrow single and dual damascene process window and they are generally quite expensive.
On the issue of interlevel dielectric (ILD) adhesion to the interlevel barrier material, this is addressed in several ways including the use of organic or inorganic adhesion promoters that chemically bind to both the ILD and diffusion barrier material thereby increasing the adhesive strength and overall mechanical integrity of the stack. In the case of organic adhesion promoters, however, the use of various ashing chemistries, while potentially capable of modifying porous OSG ILD films minimally, can consume the adhesion promoter weakening the mechanical strength of the stack and thereby degrading the reliability of the Cu/ULK interconnect structure.
In view of the drawbacks mentioned above with prior art processes of fabricating an interconnect structure which includes an OSG dielectric, there is a need for providing a new method of fabricating an interconnect structure wherein the wall portions of the OSG dielectric within a trench opening are protected such that no damage occurs thereto.